The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2019
Filed:
Jan. 19, 2016
KE Wang, Charlottesville, VA (US);
Kevin Skadron, Charlottesville, VA (US);
Mircea R. Stan, Charlottesville, VA (US);
Runjie Zhang, Charlottesville, VA (US);
Brett Meyer, Quebec, CA;
Ke Wang, Charlottesville, VA (US);
Kevin Skadron, Charlottesville, VA (US);
Mircea R. Stan, Charlottesville, VA (US);
Runjie Zhang, Charlottesville, VA (US);
Brett Meyer, Quebec, CA;
University of Virginia Patent Foundation, Charlottesville, VA (US);
Abstract
A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile 'positive charged particles' and current resources as a 'negative charged back-ground.' The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.