The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Dec. 05, 2017
Applicant:
Integrated Device Technology, Inc., San Jose, CA (US);
Inventor:
Menno Spijker, Ottawa, CA;
Assignee:
INTEGRATED DEVICE TECHNOLOGY, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/07 (2006.01); H04L 7/033 (2006.01); H04J 3/06 (2006.01); H03L 7/08 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
H03L 7/07 (2013.01); H03L 7/0805 (2013.01); H03L 7/093 (2013.01); H03L 7/0991 (2013.01); H04J 3/0641 (2013.01); H04J 3/0697 (2013.01); H04L 7/0331 (2013.01); H03L 2207/06 (2013.01); H04J 3/0667 (2013.01);
Abstract
An apparatus includes a plurality of digital phase-locked loops and a time slotted bus. The time slotted bus is configured to couple the plurality of digital phase-locked loops. The plurality of digital phase-locked loops may be configured to exchange parameters between two or more of the plurality of digital phase-locked loops using one or more time slots of the time slotted bus.