The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Jul. 05, 2012
Applicants:

Anthony Joseph Kenyon, London, GB;

Adnan Mehonic, London, GB;

Inventors:

Anthony Joseph Kenyon, London, GB;

Adnan Mehonic, London, GB;

Assignee:

UCL Business PLC, London, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/08 (2013.01); G11C 13/0002 (2013.01); G11C 13/0007 (2013.01); G11C 13/0009 (2013.01); H01L 27/2472 (2013.01); H01L 45/1233 (2013.01); H01L 45/145 (2013.01); H01L 45/1608 (2013.01); H01L 45/1625 (2013.01); H01L 45/1641 (2013.01); G11C 13/0011 (2013.01); G11C 2213/15 (2013.01); G11C 2213/33 (2013.01); G11C 2213/34 (2013.01);
Abstract

This invention relates to memory resistors, arrays of memory resistors and a method of making memory resistors. In particular, this invention relates to memory resistors having an on state and an off state, comprising: (a) a first electrode; (b) a second electrode; (c) a dielectric layer disposed between the first and second electrodes; wherein the dielectric layer comprises nanoparticles of semiconductor material, and wherein in the on state nanoparticles form at least one conductive filament encapsulated by the dielectric layer, thereby providing a conductive pathway between the first electrode and the second electrode.


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