The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Mar. 28, 2018
Applicant:
Ablic Inc., Chiba-shi, Chiba, JP;
Inventors:
Masahiro Hatakenaka, Chiba, JP;
Mitsuhiro Yoshimura, Chiba, JP;
Assignee:
ABLIC INC., Chiba, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 23/5226 (2013.01); H01L 29/0696 (2013.01); H01L 29/66734 (2013.01); H01L 29/0646 (2013.01); H01L 29/0649 (2013.01);
Abstract
A semiconductor device in which a trench in a cell outer peripheral region configured to pull out a gate electrode and a trench in a cell region having a vertical transistor are formed with the same width to enable a reduction in chip area, and a manufacturing method thereof in which a gate contact hole is formed directly on a trench in a cell outer peripheral region on a self-alignment basis, and a gate wiring electrode is connected thereto are provided.