The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Sep. 22, 2017
Electronics and Telecommunications Research Institute, Daejeon, KR;
Industry-academic Cooperation Foundation, Dankook University, Yongin-si, Gyeonggi-do, KR;
Jimin Oh, Daejeon, KR;
Yong-Seo Koo, Seoul, KR;
Yil Suk Yang, Daejeon, KR;
Jongdae Kim, Daejeon, KR;
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon, KR;
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, DANKOOK UNIVERSITY, Yongin-si, Gyeonggi-Do, KR;
Abstract
Provided are an ESD protection diode and an electronic device including the same. An ESD protection diode and an electronic device including the same according to an embodiment of the inventive concept include first to fifth wells. The first well is connected to a first voltage terminal. The second well is connected to a second voltage terminal. The third well is connected to the input/output terminal. The fourth well is disposed between the first well and the third well, and the fifth well is disposed between the second well and the third well. The first to third wells are N-type wells, and the fourth and fifth wells are P-type wells. The first well includes a first N+ diffusion region and the second well includes a second N+ diffusion region. The fourth well includes a first P+ diffusion region and the fifth well includes a second P+ diffusion region. According to an embodiment of the inventive concept, an internal circuit is protected fro an ESD pulse applied to a plurality of terminals and holding voltage is increased.