The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

May. 04, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Sunchul Kim, Asan-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 25/0657 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0652 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor package includes a first semiconductor chip on a first substrate, a first mold layer provided on the first substrate to cover a side surface of the first semiconductor chip, a solder structure provided on the first substrate, and a second substrate provided on the solder structure. A guide receptacle is formed at one of a top surface of the first mold layer and a bottom surface of the second substrate, a first alignment protrusion is formed at the other of the top surface of the first mold layer and the bottom surface of the second substrate, and at least a portion of the first alignment protrusion is provided in the guide receptacle.


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