The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

May. 09, 2018
Applicant:

Commissariat a L'energie Atomique ET Aux Energies Alternatives, Paris, FR;

Inventors:

Gabriel Molas, Grenoble, FR;

Michel Harrand, Saint-Egreve, FR;

Elisa Vianello, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 29/02 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0035 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0011 (2013.01); G11C 13/0033 (2013.01); G11C 13/0038 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 2013/009 (2013.01); G11C 2013/0076 (2013.01); G11C 2013/0078 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/32 (2013.01);
Abstract

A method for managing the endurance of a non-volatile rewritable memory including a dielectric material layer that switches between a high resistance state, with a first resistance value, and a low resistance state, with a second resistance value, the method including at least one of the following operations: at the end of each erasure operation: reading the first resistance value and comparing it with a first predetermined median resistance value, and determining the writing programming conditions from the comparison results; and at the end of each writing operation: reading the second resistance value and comparing it with a second predetermined median resistance value, and determining the erasure programming conditions from the comparison results, linking the programming conditions and the first and second read resistance values, the writing and erasure programming conditions being applied to the electrodes of the stack during the following writing and/or erasure operations.


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