The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Dec. 15, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Manabu Sakai, San Jose, CA (US);

Qui Vi Nguyen, San Jose, CA (US);

Yen-Lung Li, San Jose, CA (US);

Assignee:

SanDisk Technologies LLC, Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 16/08 (2006.01); G11C 5/14 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 8/08 (2013.01); G11C 5/148 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/30 (2013.01);
Abstract

This disclosure provides techniques for reducing leakage current in a non-volatile memory that does not include a local interconnect. In one example, a low-voltage pulse can be applied to all of the word-lines in all of the blocks of the non-volatile memory. The low-voltage pulse can be applied during a period in which the row decoder is typically idle in order to reduce the total amount of time required to program the non-volatile memory. After the conclusion low-voltage pulse, a global control line voltage can be applied at about the same level as the low-voltage pulse to keep the word-lines floating when the pulse is no longer applied.


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