The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Dec. 18, 2017
Juniper Networks, Inc., Sunnyvale, CA (US);
Venkata G Ramanan, San Jose, CA (US);
John P. Nguyen, San Jose, CA (US);
Santosh Kumar Pappu, San Jose, CA (US);
Juniper Networks, Inc., Sunnyvale, CA (US);
Abstract
A device receives void configuration information that identifies a set of rules for generating void information based on printed circuit board (PCB) design information, and receives, based on receiving the void configuration information, the PCB design information that identifies via information of a PCB. The device compares, based on receiving the PCB design information, the set of rules, associated with the void configuration information, and the via information associated with the PCB design information, and generates the void information based on comparing the set of rules, associated with the void configuration information, and the via information associated with the PCB design information. The void information includes a set of parameters associated with a set of voids to be included in the PCB. The device performs an action based on generating the void information.