The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Dec. 17, 2009
Applicants:

Minas Hambardzumyan, Plano, TX (US);

Michael J. Krasnicki, Richardson, TX (US);

Ryan W. Eatmon, Carrollton, TX (US);

Inventors:

Minas Hambardzumyan, Plano, TX (US);

Michael J. Krasnicki, Richardson, TX (US);

Ryan W. Eatmon, Carrollton, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01);
Abstract

Circuit analysis software packages are a significant tool used today in the design of integrated circuits (ICs). Many of the conventional and commercially available simulation or analysis packages, however, are limited to performing static design 'checks' using topology based search algorithms to find potential problems in a subject design. Here, a system is provided that allows a user to define parameters that comport with the subject design to generate a set of specific topologies from a set of generic topologies. These generated topologies can then be used to perform a more thorough analysis of the subject design.


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