The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Apr. 12, 2017
Applicant:

Arm Limited, Cambridge, GB;

Inventor:

Kim Richard Schuttenberg, Gilbert, AZ (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3861 (2013.01); G06F 9/30043 (2013.01); G06F 9/3842 (2013.01); G06F 9/3863 (2013.01);
Abstract

An apparatus and method are provided for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow. The apparatus comprises processing circuitry having an associated instruction set architecture, and arranged to execute software comprising instructions defined by the instruction set architecture, and control circuitry for controlling operation of the processing circuitry according to constraints defined by the instruction set architecture. The instruction set architecture defines a default recovery point constraint for determining a recovery point from which to resume instruction execution following handling of an unexpected change in instruction flow. The control circuitry is responsive to information derived from the software executing on the processing circuitry to detect a recovery point relaxation condition, and responsive to the recovery point relaxation condition, to allow determination of the recovery point unconstrained by the default recovery point constraint. Hence, the described techniques provide a mechanism by which the ISA may allow the software to inform the hardware of situations where the recovery point constraint can be relaxed, in such situations this enabling the processing circuitry to potentially execute the code with increased performance and/or reduced power consumption.


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