The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Mar. 22, 2018
Applicant:
Fanuc Corporation, Minamitsuru-gun, Yamanashi, JP;
Inventor:
Takaaki Komatsu, Yamanashi, JP;
Assignee:
FANUC CORPORATION, Yamanashi, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 12/0884 (2016.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1068 (2013.01); G06F 12/0884 (2013.01); G06F 13/4204 (2013.01); G11C 29/52 (2013.01);
Abstract
To provide a multi-rank SDRAM control method and an SDRAM controller that prevent performance degradation and minimize increase in parts count even in a multi-rank SDRAM configuration. A multi-rank SDRAM control method controls a multi-rank SDRAM formed by connecting data buses of multiple SDRAM devices. In each of the multiple SDRAM devices, only a data mask signal for a rank of the SDRAM device, which is to be accessed, is negated, whereby an access to the rank is executed.