The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 12, 2019

Filed:

Mar. 14, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Deva Sudhir Kumar Pulivendula, Hyderabad, IN;

Venkata Devarasetty, Hyderabad, IN;

Nikesh Gupta, Hyderabad, IN;

Srikanth Gudipudi, Hyderabad, IN;

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3296 (2019.01); G06F 9/4401 (2018.01); G06F 21/44 (2013.01); G06F 21/57 (2013.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 9/4406 (2013.01); G06F 21/44 (2013.01); G06F 21/575 (2013.01); G11C 11/4074 (2013.01); G11C 11/40615 (2013.01);
Abstract

A method for reducing power in a system is provided according to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collapsing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip.


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