The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Oct. 27, 2016
Nvidia Corporation, Santa Clara, CA (US);
Pavan Kumar Datla Jagannadha, Santa Clara, CA (US);
Dheepakkumaran Jayaraman, Sunnyvale, CA (US);
Anubhav Sinha, Telangana, IN;
Karthikeyan Natarajan, Fremont, CA (US);
Shantanu Sarangi, Saratoga, CA (US);
Amit Sanghani, San Jose, CA (US);
Milind Sonawane, San Jose, CA (US);
Mahmut Yilmaz, Los Altos Hills, CA (US);
Nvidia Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.