The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Oct. 26, 2017
Xilinx, Inc., San Jose, CA (US);
Alan Shu-Jen Chao, San Jose, CA (US);
Owais E. Malik, San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
An interposer block, a chip package assembly test system and method for testing a chip package assembly are described herein. In one example, an interposer block for an integrated circuit chip package test system is provided. The interposer block includes a main body, a retainer plate, and a cover plate. A plurality of spring pins are each disposed in a respective one of a plurality of spring pin receiving holes formed in the main body. The retainer plate is coupled to the main body and captures the spring pins within the plurality of spring pin receiving holes. The cover plate is movably coupled to the main body. The cover plate has a plurality of spring pin clearance holes form therethrough that align with the plurality of spring pin receiving holes formed in the main body. A spring bias the cover plate away from the main body to a position where the spring pins not an exposed through a top surface the cover plate, and where the cover plate is movable towards the main body to a position that exposes the spring pins through the top surface of the cover plate.