The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 12, 2019
Filed:
Nov. 22, 2016
Nsk Ltd., Tokyo, JP;
Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;
Shin Kumagai, Tokyo, JP;
Nobuhiko Ando, Tokyo, JP;
Kyosho Uryu, Tokyo, JP;
Takahiro Yamazaki, Tokyo, JP;
NSK LTD., Shinaeawa-ku, Tokyo, JP;
TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Minato-ku, Tokyo, JP;
Abstract
An electronic control unit where an external watch dog timer (WDT) can always normally detect an abnormality (a failure) to a micro controller unit (MCU) related to a built-in self-test (BIST) function and which can maintain safety of a system. The control unit includes an external WDT to detect an abnormality of the MCU, a reset circuit to reset the MCU when the external WDT detects the abnormality of the MCU, and an ON/OFF control section to turn a gate of the semiconductor switching device on or off in accordance with the external WDT. The inverter is stopped by turning the gate off via the ON/OFF control section when the external WDT is a disable state. When the abnormality of the MCU is not detected in an enable state, the inverter is driven by turning the gate on via the ON/OFF control section. When the abnormality of the MCU is detected, the inverter is stopped by turning the gate off via the ON/OFF control section and the MCU is reset by the reset circuit.