The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Sep. 17, 2018
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Peng Liu, Fremont, CA (US);

Zhendong Guo, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 7/02 (2006.01); H03K 17/60 (2006.01); H03K 17/10 (2006.01); H03K 19/177 (2006.01); H03K 19/00 (2006.01); H03K 17/693 (2006.01); H03K 17/62 (2006.01);
U.S. Cl.
CPC ...
H03K 17/10 (2013.01); H03K 7/02 (2013.01); H03K 17/60 (2013.01); H03K 17/6242 (2013.01); H03K 17/693 (2013.01); H03K 19/0021 (2013.01); H03K 19/17784 (2013.01);
Abstract

Linearity of a PAM-4 voltage-mode driver is improved using current compensation. The driver receives a first input data signal having a first logic level and a second input data signal having a second logic level. In an additive current mode, when the first logic level matches the second logic level, the driver uses switch circuitry to form an auxiliary current path through which supplementary current (I_Supplementary) flows from a voltage regulator. In a primary current mode, when the first logic level does not match the second logic level, the driver uses the switch circuitry to break the auxiliary current path, thereby preventing the supplementary current (I_Supplementary) from flowing from the voltage regulator.


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