The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Apr. 19, 2016
Applicant:

Sharp Kabushiki Kaisha, Sakai, Osaka, JP;

Inventor:

Hiroshi Aichi, Sakai, JP;

Assignee:

SHARP KABUSHIKI KAISHA, Sakai, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78627 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 27/127 (2013.01); H01L 27/1222 (2013.01); H01L 27/1251 (2013.01); H01L 27/1288 (2013.01); H01L 29/66757 (2013.01); H01L 29/78621 (2013.01); H01L 29/78675 (2013.01);
Abstract

A semiconductor device includes at least one thin film transistor (), the at least one thin film transistor including a semiconductor layer (A,B) which includes a channel region (A,), a high-concentration impurity region, and a low-concentration impurity region (A,B) which is located between the channel region and the high-concentration impurity region, a gate electrode (A,B) provided on a gate insulating layer (), an interlayer insulating layer () provided on the gate electrode, and a source electrode (A,B) and a drain electrode (A,B), wherein the interlayer insulating layer and the gate insulating layer have a contact hole extending to the semiconductor layer, at least one of the source electrode (A,B) and the drain electrode (A,B) being in contact with the high-concentration impurity region inside the contact hole, at a side wall of the contact hole, a side surface of the gate insulating layer is aligned with a side surface of the interlayer insulating layer, and at an upper surface of the semiconductor layer, an edge of the contact hole aligned with an edge of the high-concentration impurity region.


Find Patent Forward Citations

Aichi, Hiroshi. (2019). Semiconductor device and method for manufacturing same (U.S. Patent No. 10468533). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10468533

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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