The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Aug. 16, 2017
Applicant:

Infineon Technologies Dresden Gmbh, Dresden, DE;

Inventor:

Dmitri Alex Tschumakow, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/732 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/737 (2006.01); H01L 29/73 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66242 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/1004 (2013.01); H01L 29/66265 (2013.01); H01L 29/732 (2013.01); H01L 29/7317 (2013.01); H01L 29/7371 (2013.01); H01L 23/66 (2013.01);
Abstract

Embodiments provide a method for manufacturing a bipolar junction transistor. The method comprises a step of providing a layer stack, the layer stack comprising a semiconductor substrate having a trench isolation, a base contact layer stack, wherein the base contact layer stack comprises a recess forming an emitter window, lateral spacers arranged on sidewalls of the emitter window, the lateral spacers isolating a base contact layer of the base contact layer stack; and a base layer arranged in the emitter window on the semiconductor substrate, wherein the base layer at least partially protrudes under the lateral spacers. The method further comprises a step of providing an isolation layer on the base layer.


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