The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Nov. 11, 2016
Applicant:

Shindengen Electric Manufacturing Co., Ltd., Chiyoda-ku, Tokyo, JP;

Inventors:

Daisuke Arai, Saitama, JP;

Mizue Kitada, Saitama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/868 (2006.01); H01L 29/16 (2006.01); H01L 29/872 (2006.01); H02M 7/5387 (2007.01); H02M 3/156 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/407 (2013.01); H01L 29/7805 (2013.01); H01L 29/7813 (2013.01); H01L 29/868 (2013.01); H01L 29/872 (2013.01); H02M 3/156 (2013.01); H02M 7/5387 (2013.01);
Abstract

Provided is a MOSFET which includes: a semiconductor base substrate having an n-type column region and a p-type column region, a base region and a source region, wherein a super junction structure is formed of the n-type column region and the p-type column region; a trench having side walls and a bottom; a gate electrode formed in the trench by way of a gate insulation film; a carrier compensation electrode positioned between the gate electrode and the bottom of the trench; an insulation region separating the carrier compensation electrode from the side walls and the bottom; and a source electrode electrically connected to the source region and also electrically connected to the carrier compensation electrode. According to the MOSFET of the present invention, even when an irregularity in a charge balance occurs around the gate, an irregularity in switching characteristics when the MOSFET is turned off can be decreased.


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