The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 05, 2019
Filed:
Apr. 27, 2017
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventor:
JaeWook Yoo, Suwon-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); H01L 23/552 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/02068 (2013.01); H01L 21/4817 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 24/49 (2013.01); H01L 25/0655 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48091 (2013.01);
Abstract
A semiconductor package and a method of fabricating the same, the method including mounting semiconductor chips on a substrate; forming a mold layer that covers the semiconductor chips on the substrate; forming external terminals on a bottom surface of the substrate; forming a separation layer on the external terminals and the bottom surface of the substrate; cutting the substrate and the mold layer to separate the semiconductor chips from each other; and forming a shield surrounding the mold layer and a side surface of the substrate.