The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

May. 10, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Dianzheng Dong, Beijing, CN;

Bin Zhang, Beijing, CN;

Ming Tian, Beijing, CN;

Qiang Zhang, Beijing, CN;

Guangxing Wang, Beijing, CN;

Kan Zhang, Beijing, CN;

Pengming Chen, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G11C 19/28 (2006.01); G11C 19/18 (2006.01);
U.S. Cl.
CPC ...
G09G 3/20 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0219 (2013.01);
Abstract

The disclosure discloses a shift register unit, a driving method thereof, a gate driving circuit and a display device. The shift register unit comprises an input circuit, a reset circuit, a control circuit, a pull-down circuit and an output circuit, a first control terminal of the output circuit is coupled to a first node, its first input terminal is coupled to a second clock signal terminal, its first output terminal is coupled to a signal output terminal, both terminals of the pull-down circuit are coupled to a first clock signal terminal and the first node, respectively, and the pull-down circuit may pull down the potential of the first node via the first clock signal terminal, which may thus avoid that the potential of the first node also rises when the potential of the second clock signal terminal rises, and the signal of the second clock signal terminal is mistakenly provided to the signal output terminal to cause various poor display.


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