The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Jun. 15, 2017
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Michael Scott Allison, Longmont, CO (US);

MadhuKiran Vaddi, Fremont, CA (US);

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/10 (2016.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0629 (2013.01); G06F 3/0688 (2013.01); G06F 8/41 (2013.01); G06F 12/0246 (2013.01); G06F 12/0653 (2013.01); G06F 2212/1056 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A system and an operating method thereof include a system on chip (SOC) flash controller having at least one SOC channel; at least one memory device coupled with the at least one SOC channel; a printed circuit board (PCB), wherein the SOC flash controller and the at least one memory device are mounted thereon; a flash address translation (FTL) address translator automatically managing the at least one memory device in accordance with a PCB board configuration file of the PCB board and a drive configuration file of the at least one memory device; and a fuse storing an open data plane (ODP) fuse setting generated in accordance with at least in part with data of the PCB board configuration file and the drive configuration file.


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