The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Nov. 19, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jesse P. Arroyo, Rochester, MN (US);

Christopher J. Engel, Rochester, MN (US);

Kaveh Naderi, Austin, TX (US);

James E. Smith, Georgetown, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/16 (2006.01); G06F 11/20 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1616 (2013.01); G06F 11/2005 (2013.01); G06F 11/2007 (2013.01); G06F 11/2017 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 2201/805 (2013.01); G06F 2201/85 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A method, system and computer program product are provided for implementing cable failover in multiple cable Peripheral Component Interconnect Express (PCIE) IO interconnections to an external IO enclosure. System firmware is provided for implementing health check functions for the PCIE IO interconnections to identify a faulted low byte cable. A cable failover mechanism recovers a PCI link to the external IO enclosure. A multiplexer logic is provided between the PCIE host bridge (PHB) and the cable connected to the IO enclosure to perform a full lane reversal of the PCIE lanes.


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