The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Jul. 29, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Deepak Mathew, Acton, MA (US);

Ajay Anant Ingle, Austin, TX (US);

Yurong Sun, Acton, MA (US);

Jianming Zhu, Acton, MA (US);

Marc Hoffman, Mansfield, MA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/483 (2006.01); G06F 17/17 (2006.01); G06F 9/30 (2018.01); G06F 7/544 (2006.01); G06F 1/03 (2006.01); G06F 7/548 (2006.01);
U.S. Cl.
CPC ...
G06F 7/483 (2013.01); G06F 1/03 (2013.01); G06F 7/544 (2013.01); G06F 9/30036 (2013.01); G06F 17/17 (2013.01); G06F 7/548 (2013.01);
Abstract

An apparatus includes one or more registers configured to store a vector of input values. The apparatus also includes a coefficient determination unit configured to, responsive to execution by a processor of a single instruction, select a plurality of piecewise analysis coefficients. The plurality of piecewise analysis coefficients includes one or more sets of piecewise analysis coefficients, and each set of piecewise analysis coefficients corresponds to an input value of the vector of input values. The apparatus further includes arithmetic logic circuitry configured to, responsive to the execution of at least the single instruction, determine estimated output values of a function based on the plurality of piecewise analysis coefficients and the vector of input values.


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