The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 05, 2019

Filed:

Mar. 24, 2017
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventors:

Shay Benisty, Beer Sheva, IL;

Eran Erez, Bothell, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/24 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0688 (2013.01); G06F 13/24 (2013.01); G06F 2213/2406 (2013.01);
Abstract

Systems and methods for dynamic and adaptive interrupt coalescing are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device notifies the host device, via an interrupt, of entries on the completion queue. However, excessive interrupts become a burden to the host device. In that regard, the memory device includes a dynamic and adaptive interrupt coalescing methodology according to one or more parameters including: the completion queue; the commands; the queue depth; latency; and memory device firmware settings. In this way, the memory device may reduce the number of interrupts while still notifying the host device in a timely manner.


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