The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Aug. 08, 2018
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventors:

Noam Eshel, Pardesia, IL;

Golan Zeituni, Kfar-Saba, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); G11C 27/02 (2006.01); H04N 5/357 (2011.01);
U.S. Cl.
CPC ...
H04N 5/3575 (2013.01); G11C 27/026 (2013.01); H04N 5/378 (2013.01);
Abstract

A sample-and-hold circuit comprises a sampling capacitor; an amplifier transistor; and a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including: an auto-zero phase in which the feedback capacitor is discharged, a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor, an integration phase in which the integration capacitor is charged, and a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.


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Eshel, Noam. (2019). Sample-and-hold circuit with feedback and noise integration (U.S. Patent No. 10462397). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10462397

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