The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Sep. 17, 2018
Applicant:

Fujitsu Limited, Kanagawa, JP;

Inventors:

Biaodong Cai, San Ramon, CA (US);

Richard Dunsmore, McKinney, TX (US);

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 3/16 (2006.01); H04L 12/64 (2006.01); H04L 12/863 (2013.01); H04L 12/865 (2013.01); H04L 12/707 (2013.01); H04L 12/947 (2013.01); H04L 12/931 (2013.01); H04L 12/935 (2013.01); H04L 12/933 (2013.01); H04L 12/741 (2013.01); H04L 12/801 (2013.01); H04B 10/00 (2013.01); H04Q 11/00 (2006.01); H04J 14/02 (2006.01);
U.S. Cl.
CPC ...
H04J 3/1658 (2013.01); H04L 12/64 (2013.01); H04L 45/24 (2013.01); H04L 45/745 (2013.01); H04L 47/12 (2013.01); H04L 47/623 (2013.01); H04L 47/6225 (2013.01); H04L 47/6275 (2013.01); H04L 49/1546 (2013.01); H04L 49/25 (2013.01); H04L 49/3045 (2013.01); H04L 49/351 (2013.01); H04B 10/00 (2013.01); H04J 14/0212 (2013.01); H04Q 2011/0016 (2013.01); H04Q 2011/0086 (2013.01);
Abstract

Systems and Methods for switching optical data units (ODUs) and Internet Protocol (IP) packets as Ethernet packets in an optical transport network (OTN), IP, and Ethernet switching system. The OTN, IP, and Ethernet switching system may include an Ethernet fabric having a set of M Ethernet switches each including a set of N switch ports, and a set of N input/output (IO) devices each including a set of W IO ports, a set of M Ethernet ports, an IO side packet processor (IOSP), and a fabric side packet processor (FSP). Each Ethernet switch may establish switch queues. Each IO device may establish a set of M hierarchical virtual output queues each including a set of N ingress-IOSP queues and ingress-virtual output queues, a set of W egress-IOSP queues, a set of M ingress-FSP queues, and a set of N hierarchical virtual input queues each including a set of N egress-FSP queues and egress-virtual input queues.


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