The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Aug. 01, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mohammad Meysam Zargham, San Diego, CA (US);

Yan Wang, San Diego, CA (US);

Li Lu, San Diego, CA (US);

Dinesh Jagannath Alladi, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0617 (2013.01); H03M 1/002 (2013.01);
Abstract

Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.


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