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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10461195 B1

PDFFull Text
Date of Patent:
Oct. 29, 2019

Filed:

Jan. 08, 2018

Semiconductor devices

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Taesoon Duyeon Kwon, Suwon-si, KR;

JeongYun Lee, Yongin-si, KR;

A-reum Ji, Hwaseong-si, KR;

Kyungseok Min, Yongin-si, KR;

GeumJung Seong, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Matthew L Reames

Assistant Examiner:

John A Bodnar

Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01); H01L 29/66 (2006.01); B82Y 10/00 (2011.01); H01L 29/417 (2006.01); H01L 29/775 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78618 (2013.01); B82Y 10/00 (2013.01); H01L 21/02603 (2013.01); H01L 21/764 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/41725 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/7845 (2013.01); H01L 29/78696 (2013.01); H01L 29/165 (2013.01); H01L 29/7848 (2013.01);
Abstract

Disclosed is a semiconductor device. The semiconductor device includes a substrate, channel semiconductor patterns vertically stacked and spaced apart from each other on the substrate, a gate electrode running across the channel semiconductor patterns, source/drain regions at opposite sides of the gate electrode, the source/drain regions being connected to the channel semiconductor patterns, and air gaps between the substrate and bottom surfaces of the source/drain regions so that the bottom surfaces of the source/drain regions do not contact the substrate.

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