The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Jan. 03, 2017
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, Kanagawa, JP;

Inventor:

Takashi Katsuki, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/049 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49861 (2013.01); H01L 23/049 (2013.01); H01L 23/49811 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19107 (2013.01);
Abstract

In a semiconductor device, first to fourth circuit patterns are formed on an insulating substrate in a case. A first end of a first lead frame is connected via solder to the first circuit pattern and another end of the first lead frame extends outside from the case. In the same way, a first end of a second lead frame is connected via solder to the fourth circuit pattern and another end extends outside from a case. Portions of the second and third circuit patterns are covered by the first lead frame and are respectively buried by insulating layers. In addition, a semiconductor element is provided via solder on a region of the first lead frame above the first circuit pattern. Wires electrically connect the semiconductor element and a region of the second lead frame above the fourth circuit pattern.


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