The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

May. 10, 2018
Applicant:

Renesas Electronics Corporation, Koto-ku, Tokyo, JP;

Inventors:

Motoo Suwa, Tokyo, JP;

Takafumi Betsui, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Koto-ku, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); G11C 11/4076 (2006.01); H01L 27/108 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 5/063 (2013.01); H01L 23/498 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/49844 (2013.01); H01L 23/5381 (2013.01); H01L 23/5383 (2013.01); H01L 27/108 (2013.01); H01L 23/5386 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract

To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.


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