The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Aug. 21, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventor:

Jong-pil Son, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/04 (2006.01); G01R 31/3185 (2006.01); G06F 12/02 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01); H01L 21/66 (2006.01); H01L 25/065 (2006.01); G11C 29/44 (2006.01); G11C 29/00 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G11C 5/04 (2013.01); G01R 31/318513 (2013.01); G01R 31/318555 (2013.01); G06F 12/0207 (2013.01); G11C 7/1006 (2013.01); G11C 7/1051 (2013.01); G11C 7/18 (2013.01); G11C 29/023 (2013.01); G11C 29/1201 (2013.01); G11C 29/4401 (2013.01); G11C 29/702 (2013.01); H01L 22/22 (2013.01); H01L 25/0657 (2013.01); G01R 31/3187 (2013.01); G11C 7/1012 (2013.01); G11C 2029/4402 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32225 (2013.01);
Abstract

A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line.


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