The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Oct. 17, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Ashish Sirasao, San Jose, CA (US);

Elliott Delaye, San Jose, CA (US);

Aaron Ng, San Jose, CA (US);

Ehsan Ghasemi, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/20 (2006.01); G06T 1/60 (2006.01); H04N 21/2381 (2011.01); G06F 3/03 (2006.01); H03K 19/177 (2006.01); H04N 5/30 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06T 1/20 (2013.01); G06F 3/03 (2013.01); G06T 1/60 (2013.01); H03K 19/1776 (2013.01); H04N 5/30 (2013.01); H04N 21/2381 (2013.01); G06F 12/00 (2013.01);
Abstract

An example preprocessor circuit for formatting image data into a plurality of streams of image samples includes: a plurality of memory banks configured to store the image data; multiplexer circuitry coupled to the memory banks; a first plurality of registers coupled to the multiplexer circuitry; a second plurality of registers coupled to the first plurality of registers, outputs of the second plurality of registers configured to provide the plurality of streams of image samples; and control circuitry configured to generate addresses for the plurality of memory banks, control the multiplexer circuitry to select among outputs of the plurality of memory banks, control the first plurality of registers to store outputs of the second plurality of multiplexers, and control the second plurality of registers to store outputs of the first plurality of registers.


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