The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Dec. 18, 2018
Applicant:

Sas Institute Inc., Cary, NC (US);

Inventors:

Charles S. Shorb, Cary, NC (US);

James P. Carroll, Cary, NC (US);

Assignee:

SAS Institute Inc., Cary, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 3/06 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 9/52 (2006.01); G06F 11/34 (2006.01); G06F 11/30 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1441 (2013.01); G06F 3/065 (2013.01); G06F 3/0622 (2013.01); G06F 3/0631 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01); G06F 9/5022 (2013.01); G06F 9/526 (2013.01); G06F 11/3034 (2013.01); G06F 11/3409 (2013.01); G06F 12/0246 (2013.01); G06F 2201/88 (2013.01);
Abstract

A computing device receives, at a scheduler of the computing device, a first write request from a first thread of a plurality of threads. The scheduler schedules access for the plurality of threads across a boundary of an access-controlled region in a memory of the computing device. The computing device determines that a second memory region in the access-controlled region is allocated for storing data copied from a first memory region. During copying, to the second memory region, the data copied from the first memory region, the computing device permits scheduling, by the scheduler, an operation to read from the first memory region for any read requests from the plurality of threads during the copying; and denies scheduling, by the scheduler, an operation to write to the first memory region for any subsequent write requests from the plurality of threads during the copying.


Find Patent Forward Citations

Shorb, Charles. (2019). Scheduling operations in an access-controlled region of memory (U.S. Patent No. 10459849). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10459849

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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