The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Jun. 27, 2017
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

James M. Higgins, Chandler, AZ (US);

Rodney Brittner, San Jose, CA (US);

Steven Sprouse, San Jose, CA (US);

David George Dreyer, Rochester, MN (US);

Mark D. Myran, Trabuco Canyon, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 12/0238 (2013.01); G06F 12/0638 (2013.01); G06F 2212/205 (2013.01); G06F 2212/7201 (2013.01); G11C 29/52 (2013.01);
Abstract

The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.


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