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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10459724 B1

PDFFull Text
Date of Patent:
Oct. 29, 2019

Filed:

Jul. 17, 2018

Memory device, and data processing method based on multi-layer rram crossbar array

Applicants:

Huawei Technologies Co., Ltd., Shenzhen, Guangdong, CN;

Nanyang Technological University, Singapore, SG;

Inventors:

Hao Yu, Singapore, SG;

Yuhao Wang, Singapore, SG;

Junfeng Zhao, Shenzhen, CN;

Wei Yang, Hangzhou, CN;

Shihai Xiao, Moscow, RU;

Leibin Ni, Singapore, SG;

Assignees:

HUAWEI TECHNOLOGIES CO., LTD., Shenzhen, CN;

NANYANG TECHNOLOGICAL UNIVERSITY, Singapore, SG;

Attorney:

Huawei Technologies Co., Ltd.

Primary Examiner:

Tan V Mai

Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 17/16 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01); G11C 5/02 (2006.01); G06F 7/00 (2006.01); G06F 13/00 (2006.01); G06N 3/063 (2006.01); G06J 1/00 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30036 (2013.01); G06F 7/00 (2013.01); G06F 9/3001 (2013.01); G06F 9/30025 (2013.01); G06F 13/00 (2013.01); G06F 17/16 (2013.01); G06J 1/00 (2013.01); G06N 3/0635 (2013.01); G11C 5/02 (2013.01); G11C 7/1006 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 2213/71 (2013.01); G11C 2213/77 (2013.01);
Abstract

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ror Rto indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

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