The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Nov. 18, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Katsushige Matsubara, Tokyo, JP;

Seiji Mochizuki, Tokyo, JP;

Ryoji Hashimoto, Tokyo, JP;

Toshiyuki Kaya, Tokyo, JP;

Kimihiko Nakazawa, Tokyo, JP;

Takahiro Irita, Tokyo, JP;

Tetsuji Tsuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 7/544 (2006.01); H04N 19/423 (2014.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0638 (2013.01); G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 7/544 (2013.01); H04N 19/423 (2014.11); G06F 2207/544 (2013.01);
Abstract

Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.


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