The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

Jan. 17, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Raghavendra Srinivas, Blacksburg, VA (US);

Uday Shankar Mudigonda, Bengaluru, IN;

Giby Samson, San Diego, CA (US);

Ramaprasath Vilangudipitchai, San Diego, CA (US);

Dorav Kumar, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 17/28 (2006.01); G06F 1/32 (2019.01); G06F 1/3234 (2019.01); H03K 17/693 (2006.01); H03K 17/284 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); H03K 17/284 (2013.01); H03K 17/693 (2013.01); H03K 19/0016 (2013.01);
Abstract

In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.


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