The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2019

Filed:

May. 31, 2017
Applicant:

Konica Minolta Laboratory U.s.a., Inc., San Mateo, CA (US);

Inventors:

Thien Nguyen, San Mateo, CA (US);

Sarma Sista, Menlo Park, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/324 (2019.01); G06F 13/42 (2006.01); G06F 1/3287 (2019.01); G06F 1/3234 (2019.01); G06F 13/38 (2006.01); G06F 1/3296 (2019.01); G06F 1/3203 (2019.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/3253 (2013.01); G06F 1/3287 (2013.01); G06F 1/3296 (2013.01); G06F 13/385 (2013.01); G06F 13/4282 (2013.01); G06F 1/3203 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A low frequency power management bus, a method of power management of a device, and a non-transitory computer readable program code configured to execute a power management process for a device are disclosed. The power management bus including a bus, and a plurality of power nodes connected to the bus, each of the plurality of power nodes including power management control logic, a power regulator, and a power policy, and wherein the plurality of power nodes are arranged in a topology with at least one node of the plurality of nodes being designated as a super power node, the super power node configured to be connected either directly or through another power node to each of the plurality of power nodes within the topology.


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