The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Mar. 09, 2018
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Hynek Saman, Beroun, CZ;

James Thomas Deas, Edinburgh, GB;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04R 19/04 (2006.01); H04R 19/00 (2006.01); H03F 3/45 (2006.01); H03F 3/187 (2006.01); H03F 1/26 (2006.01); H03F 3/50 (2006.01);
U.S. Cl.
CPC ...
H04R 19/04 (2013.01); H03F 1/26 (2013.01); H03F 3/187 (2013.01); H03F 3/45475 (2013.01); H03F 3/45636 (2013.01); H03F 3/505 (2013.01); H04R 19/005 (2013.01); H03F 2200/03 (2013.01); H03F 2200/213 (2013.01); H04R 2201/003 (2013.01);
Abstract

An amplifier circuit has a transducer biasing node for outputting a transducer bias voltage for biasing the capacitive transducer and a signal node for receiving the input signal. An amplifier arrangement comprising a feedback resistor network provides an amplified output signal. A voltage buffer provides a buffered bias voltage at a buffer node which is connected to a terminal of the feedback resistor network, to at least partly define the quiescent level of the output signal. The buffer node is electrically coupled to the transducer biasing node via a capacitance which may form part of a bias filter.


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