The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Oct. 30, 2018
Applicant:

Silicon Mobility, Valbonne/Sophia Antipolis, FR;

Inventors:

Grégorie Martin, Valbonne, FR;

David Cavalli, Cagnes sur Mer, FR;

Fabian Firmin, Nice, FR;

Assignee:

Silicon Mobility, Valbonne/Sophia Antipolis, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/177 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017581 (2013.01); G06F 17/5031 (2013.01); G06F 17/5054 (2013.01); G06F 17/5072 (2013.01); H03K 19/17704 (2013.01); H03K 19/17724 (2013.01);
Abstract

An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs by abutment of an out pin to an adjacent in pin. Each ACLB may be an instance of multiple programmable functional blocks. Each ACLB may be a particular ACLB type that provides a particular instance of the multiple programmable functional blocks. The EFPGA may include several ACLBs of the same type. An ACLB of one type may be adjacent an ACLB of a different type. The ACLBs may form sets that are configured identically. The sets may be interconnected by abutment of an out pin to an adjacent in pin. The EFPGA may be part of a system-on-chip integrated circuit. A method for designing an EFPGA with ACLBs that are interconnected by abutment is disclosed.


Find Patent Forward Citations

Martin, Grégorie. (2019). Embedded fpga with multiple configurable flexible logic blocks instantiated and interconnected by abutment (U.S. Patent No. 10454480). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10454480

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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