The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Sep. 05, 2017
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventor:

Masayuki Usuda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/2885 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/2885 (2013.01); H03K 3/012 (2013.01); H03K 3/0375 (2013.01); H03K 3/356034 (2013.01); H03K 3/356052 (2013.01);
Abstract

A latch circuit includes first and second NAND circuits and first and second capacitive elements. The first NAND circuit has a first input node into which a first signal is input. The second NAND circuit has a first input node into which a second signal is input, a second input node which is connected to an output node of the first NAND circuit, and an output node which is connected to a second input node of the first NAND circuit. The first capacitive element has one end connected to the first input node of the first NAND circuit and has another end connected to the output node of the first NAND circuit. The second capacitive element has one end connected to the first input node of the second NAND circuit and has another end connected to the output node of the second NAND circuit.


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