The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

May. 18, 2017
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Daisuke Ichikawa, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/063 (2013.01); H01L 29/0696 (2013.01); H01L 29/0878 (2013.01); H01L 29/404 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01);
Abstract

A semiconductor device includes: a semiconductor substrate with a first conductivity type; a semiconductor layer with a second conductivity type formed on the semiconductor substrate; a drain region with the second conductivity type and a source region with the second conductivity type formed to be spaced apart from each other in a surface region of the semiconductor layer; a drain buffer region with the second conductivity type formed in the semiconductor substrate directly under the drain region and in the semiconductor layer; a conductivity type well region with the second conductivity type formed on the semiconductor layer between the drain region and the drain buffer region; and a drain metal formed on the drain region to be electrically connected to the drain region and to overlap the well region in a plan view.


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