The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Apr. 27, 2018
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Myoung Geun Cha, Seoul, KR;

Sang Gun Choi, Suwon-si, KR;

Thanh Tien Nguyen, Seoul, KR;

Kyoung Won Lee, Seoul, KR;

Yong Su Lee, Seoul, KR;

Joo Hye Jung, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01);
U.S. Cl.
CPC ...
H01L 27/3276 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); H01L 27/3262 (2013.01); H01L 27/3265 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0262 (2013.01);
Abstract

A display device includes first semiconductor pattern including a first channel portion, a first electrode connected to a driving voltage line, and a second electrode connected to a light emitting element, a first insulating, a first conductive layer including a first gate electrode, a second insulating layer, a second conductive layer including an initialization power line, a third insulating layer, an upper semiconductor layer including a second semiconductor pattern including a second channel portion, a third electrode, and a fourth electrode connected to the first gate electrode, and a third semiconductor pattern including a third channel portion, a fifth electrode connected to the third electrode, and a sixth electrode connected to the second electrode, a fourth insulating layer, and a third conductive layer including a scan line and a control signal line, wherein the upper semiconductor layer does not overlap the first gate electrode and the initialization power line.


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