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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10453853 B1

PDFFull Text
Date of Patent:
Oct. 22, 2019

Filed:

Jul. 28, 2016

Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

Applicant:

Thin Film Electronics Asa, Oslo, NO;

Inventors:

Christer Karlsson, Linköping, SE;

Olle Jonny Hagel, Linköping, SE;

Jakob Nilsson, Linköping, SE;

Per Bröms, Linköping, SE;

Assignee:

THIN FILM ELECTRONICS ASA, Oslo, NO;

Attorneys:

Moore & Van Allen PLLC

Jeffrey R. Grey

Primary Examiner:

Daniel Whalen

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11507 (2017.01); G11B 9/02 (2006.01); H01L 27/11502 (2017.01); H01L 51/05 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); G11C 11/16 (2006.01); H01L 23/00 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); H01L 27/02 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11507 (2013.01); G11B 9/02 (2013.01); G11C 11/161 (2013.01); H01L 23/562 (2013.01); H01L 27/0248 (2013.01); H01L 27/11502 (2013.01); H01L 27/1203 (2013.01); H01L 28/40 (2013.01); H01L 28/55 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01L 51/0591 (2013.01); G11C 11/22 (2013.01); H01L 28/75 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A ferroelectric memory cell () and a memory device () comprising one or more such cells (). The ferroelectric memory cell comprises a stack () of layers arranged on a flexible substrate (). Said stack comprises an electrically active part () and a protective layer () for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer () and a top electrode layer () and at least one ferroelectric memory material layer () between said electrodes. The stack further comprises a buffer layer () arranged between the top electrode layer () and the protective layer (). The buffer layer () is adapted for at least partially absorbing a lateral dimensional change (ΔL) occurring in the protective layer () and thus preventing said dimensional change (ΔL) from being transferred to the electrically active part (), thereby reducing the risk of short circuit to occur between the electrodes.

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