The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Sep. 27, 2018
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Yohei Sawada, Tokyo, JP;

Makoto Yabuuchi, Tokyo, JP;

Yuichiro Ishii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/417 (2006.01); G11C 11/41 (2006.01); G11C 11/412 (2006.01); G11C 11/413 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 11/417 (2013.01); G11C 11/41 (2013.01); G11C 11/412 (2013.01); G11C 11/413 (2013.01); G11C 5/148 (2013.01);
Abstract

A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.


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