The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Feb. 08, 2019
Applicant:

Poynt Co., Palo Alto, CA (US);

Inventors:

Osama Bedier, Palo Alto, CA (US);

Ray Tanaka, Palo Alto, CA (US);

Robert Hernandez, Palo Alto, CA (US);

Assignee:

Poynt Co., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06K 5/00 (2006.01); G06Q 20/20 (2012.01); G07G 1/00 (2006.01); G06K 7/00 (2006.01); G07G 1/01 (2006.01); G06Q 20/04 (2012.01); G06Q 20/38 (2012.01); G06Q 20/08 (2012.01); G06Q 20/10 (2012.01); G06Q 20/40 (2012.01); G06F 3/041 (2006.01); G06F 3/14 (2006.01);
U.S. Cl.
CPC ...
G06Q 20/204 (2013.01); G06K 7/0004 (2013.01); G06Q 20/0453 (2013.01); G06Q 20/085 (2013.01); G06Q 20/102 (2013.01); G06Q 20/108 (2013.01); G06Q 20/20 (2013.01); G06Q 20/209 (2013.01); G06Q 20/382 (2013.01); G06Q 20/401 (2013.01); G06Q 20/4016 (2013.01); G07G 1/0009 (2013.01); G07G 1/0018 (2013.01); G07G 1/01 (2013.01); G06F 3/041 (2013.01); G06F 3/1423 (2013.01);
Abstract

A payment terminal, including: a display, an input device configured to generate input signals indicative of a user input, a payment instrument reader configured to receive payment instrument data from a financial payment instrument, a secure processor connected to the payment instrument reader, a main processor connected to the display, the main processor separate and distinct from the secure processor, a secure input processor connected to the input device and the secure processor, wherein the secure processor is operable between an unsecured mode, wherein the secure processor sends input coordinates based on the input signals received from the secure input processor to the main processor; and a secured mode, wherein the secure input processor ceases input coordinate forwarding to the main processor.


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