The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2019

Filed:

Nov. 26, 2008
Applicants:

William E. Hall, Clinton, CT (US);

Stefan P. Jackowski, Endicott, NY (US);

Inventors:

William E. Hall, Clinton, CT (US);

Stefan P. Jackowski, Endicott, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/55 (2013.01); G06F 21/78 (2013.01); G06F 21/81 (2013.01);
U.S. Cl.
CPC ...
G06F 21/554 (2013.01); G06F 21/78 (2013.01); G06F 21/81 (2013.01); G06F 2221/2143 (2013.01);
Abstract

A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.


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