Technique for distributing routing into superfluous metal section of an integrated circuit

Abstract

A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. A place and route tool is then employed to generate the layout by determining a placement of the determined cells and performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells. The cell library provides cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell. Each cell has cell definition data, and the cell definition data of one or more cells is arranged to identify at least one superfluous metal section as being available for routing. During performance of the routing operation, the place and route tool then references the cell definition data of the determined cells so as to take into account, when determining the routing paths, availability of any superfluous metal sections for routing. This can significantly increase the options available to the place and route tool when determining the appropriate routing paths.